Programmable logic devices (PLDs) are well-known general-purpose devices that may be programmed by a user to implement a variety of selected functions. One example of a PLD is a field programmable gate array (FPGA). An FPGA may include an array of configurable logic blocks, a plurality of input/output blocks, and block RAM elements selectively connected to each other by a programmable interconnect structure.
A user may capture a PLD design with one or more software design tools. The software design tools allow the user to specify desired functions and/or behaviors of the PLD. The user's design may target or specify one or more specific logic blocks within the PLD to implement the desired functions and/or behaviors. Additionally, the software design tools may simulate, place, and route the user's design, and generate an associated configuration file. The configuration file may be a bitwise representation of the user's design that may be used to program configurable elements within the PLD when the PLD is powered on.
In some instances, a user's PLD design may include a design core. A design core may implement, for example, a particular function or feature that may encompass several logic blocks, input/output blocks, RAM elements, and the like of the PLD. Design cores, and more particularly large and complex design cores, may require substantial design time to describe and implement through the software design tools. For example, it may take hours or days to input, simulate (e.g., verify timing and/or operating frequency), place and route a particular design core.
In some instances, the user may wish to “relocate” the design core, Relocating the design core may include changing the location of the design core within the PLD or, in some cases, moving the design core to a different PLD altogether. Traditional approaches may require the user to re-run the software design tool to specify the new design core location, simulate, place, and route the updated design. Re-running the design tool may negatively increase design time, especially when the design core is large and/or complex. Therefore, there is a need for a more efficient process to relocate all or part of a design within a PLD while providing predictable timing and/or maximum operating frequency.